High speed digital ICs are used in Serializer/Deserializer (SerDes) systems. Today's high-speed SerDes systems require use of equalizers to ensure signal integrity in the system. In these systems, a lossy channel exists between a transmitter circuit and the receiver circuit, and at high data rates, the received data stream is severely distorted and requires reconstruction (e.g., equalization) before use. During transmission of bit streams into and out of a channel, rapidly alternating zeros and ones of the signal do not reach their full steady state values at the receiver due a lossy characteristic of the channel. This causes an output data stream that is much more distorted than the input data. As a result, the data needs to be reconstructed or equalized for the received data to become usable.
Analog-to-Digital Converters (ADC)-based high speed serial link receivers offer an opportunity for applying advanced signal equalization techniques via digital signal processing (DSP) and, therefore, enable reliable communications at high data rates via lossy channels. Pulse-amplitude-modulation with four amplitude levels (“PAM-4”) signal schemes are suitable for data rate beyond 56 Gbps as most backplane channels have excessive loss at 28 GHz. A PAM-4 signal is a form of signal modulation where the message information is encoded in the amplitude of a series of signal pulses. In some cases, ADC-based PAM4 receivers may be well suited for 50+ Gbps serial data communication for various systems, from short reach (e.g., die-to-die) application to long reach application (e.g., through backplanes).
In some cases, to reduce quantization noise and to improve serial link bit-error rate (BER), baud-rate ADC requires a certain resolution (number of bits). Currently, all available SerDes ADCs use a fixed resolution (fixed number of bits). For example, a 6-bit to 8-bit resolution may be used to handle long reach channels.
In certain application, the resolution of an ADC may be made higher. However, higher resolution of ADC comes with a heavy power efficiency penalty in that the ADC itself as well as its DSP will need to consume significantly more power. This may not be justified when the receiver is used in the short reach or medium reach applications when the finite impulse response and analog equalizer therein alone are sufficient to recover the data eye.